This invention relates to a method and an apparatus for multiplying the output frequency of an oscillator, and is particularly concerned with cascading frequency doublers to provide frequency sources in the microwave and millimeter-wave frequency bands.
Emerging high-data-rate wireless communication systems in the Ka band, require highly-stabilized, low phase-noise signal sources, and the phase-locked oscillator (PLO) is considered a promising candidate. The construction of millimeter-wave PLOs, however, necessitates a complex circuitry consisting of several radio frequency (RF) components, often resulting in a cumbersome packaging and high total cost along with high DC power consumption. Recently, millimeter-wave injection-locked oscillators have been investigated to exploit low-GHz synthesizer sources comprised with low-cost ICs, as reported in:
Kamogawa et al., xe2x80x9cInjection-locked oscillator chain: a possible solution to millimeter-wave MMIC synthesizers,xe2x80x9d 1996 IEEE MTT-S Symposium Digest, pp. 517-520; and Suematsu et aL, xe2x80x9cMillimeter-wave HBT MMICs synthesizers using sub-harmonically injection-locked oscillators,xe2x80x9d 1997 IEEE GaAs IC Symposium Digest, pp. 271-274. These methods, using high multiplication factors, are also an attractive means of
attaining better performance because the phase noise deterioration for frequency multiplication varies according to f2, while the phase noise of microwave and millimeter-wave oscillators reportedly degrades according to f4-f5, as indicated in:
Isots et aL, xe2x80x9cOverview of millimeter-wave monolithic circuits,xe2x80x9d 27th European Microwave Conference Proceedings, pp. 1316-1322 (Sept. 1997).
As an alternative to millimeter-wave PLOs, frequency multipliers have been conventionally employed following microwave PLOs. In order to achieve higher orders of multiplication, frequency multipliers are often constructed with chains of frequency doublers because frequency doubling has been preferred for its higher conversion efficiency. In such multipliers, diodes have been conventionally used as devices for frequency conversion, and is required the insertion of driving power amplifiers between doublers to compensate for the conversion losses accompanied by frequency multiplication.
Although possible conversion gain is expected by using transistors such as field-effect transistors (FETs), interstate amplifiers have been needed in high frequency ranges such as millimeter-wave frequencies where small-power devices have been used as reported in:
H. Wang, et aL, xe2x80x9cA W-band source module using MMICs,xe2x80x9d IEEEE Trans. Microwave Theory Tech., Vol MTT-43, No. 5, pp. 1010-1016, May 1995.
Depending on the capabilities of the devices and the operating frequency, frequency doublers have been cascaded without driving amplifiers as reported in:
Ninomiya et aL, xe2x80x9c60-GHz transceiver for high-speed wireless LAN system,xe2x80x9d 1996 IEEE MTT-S Symposium Digest, pp. 1171-1174; and
Hamada et al, xe2x80x9c60GHz phase locked oscillator using frequency doublerxe2x80x9d, 1997
IEICE Spring Conference C-2-45. However, in these systems, each stage has been an independent circuit whose input/output impedances are matched to 50 ohms at the respective frequencies.
A configuration of cascaded frequency doublers in accordance with the prior art is illustrated in FIG. 1. A first-stage frequency doubler 1 contains in a series connection a first input matching network 1a to provide 50 ohm matching for the fundamental frequency signal, a first transistor 1b, a first quarter-wavelength open-ended stub 1c for suppressing the fundamental frequency, followed by a first output matching network 1d to provide 50 ohm matching for the second harmonic frequency signal. A second-stage frequency doubler 2 contains in a series connection a second input matching network 2a to provide 50 ohm matching for the second harmonic frequency signal, a second transistor 2b, a second quarter-wavelength open-ended stub for 2c for suppressing the second harmonic frequency, followed by a second output matching network 2d to provide 50 ohm matching for the fourth harmonic frequency signal. U.S. Pat. No. 4,754,229 issued to Kawakami and Kudo on Jun. 28, 1988 describes a microwave design of a matching circuit having similar components to those shown in FIG. 1.
The configuration shown in FIG. 1 consists of cascaded frequency doublers where each stage is designed independently so that input/output impedances at each stage is matched to provide 50 ohm termination for its corresponding frequency. As a consequence, different stubs are required for matching 50 ohm in each input/output impedance matching network. Since relatively small-power devices are used, the power level is at most approximately 0 dBm. Employing medium-power transistors for increasing the driving power level results in the frequency bandwidth becoming narrower. This is because the input resistance of medium-power transistors, which is originally relatively low, is often even further lowered by a quarter-wavelength open-ended stub for suppressing the fundamental frequency, necessitating a larger transforming ratio to 50 ohm. For instance, a GaAs-based 500 xcexcm PHEMT from Northrop Grumman Corporation shows the input resistance of approximately 5 ohm, hence the transforming ratio to 50 ohm is about 10. This ratio can become equivalently even higher by the effect of the quarter-wavelength open-ended stub. In the case of such large ratios, an additional impedance matching network may need to be employed if the circuit is to be terminated to 50 ohms with a sensible frequency bandwidth.
It is an object of the present invention to provide a method and an apparatus for multiplying the output frequency of an oscillator in low-frequency microwave bands.
It is another object of the invention to provide a highly stable, low-phase-noise local frequency source in microwave and millimeter-wave frequency bands.
Therefore, in accordance with an aspect of the present invention, there is provided a method of frequency multiplication comprising the steps of:
(a) receiving an input signal having a fundamental frequency component f0;
(b) providing an input impedance matching to said fundamental frequency component;
(c) performing a plurality of n frequency doubling operations in series to derive from the input signal an output signal having an output frequency component of 2nf0, wherein each frequency doubling operation, hereby referred to as k"" th doubling operation Kxe2x89xa6n, includes the steps of
receiving a kxe2x80x2 th input signal having an input frequency component of 2(k-1)f0,
deriving from the kxe2x80x2 th input signal a kxe2x80x2 th intermediate signal having a harmonic frequency component of 2kf0,
suppressing the input frequency component of 2(k-1)f0 from the intermediate signal; and
(d) providing an interstage impedance matching to the harmonic frequency component of 2kf0 between each pair of consecutive k"" th and (k+1)xe2x80x2th frequency doubling operations; and
(e) providing an output impedance matching to the output frequency component of 2nf0. Preferably, each doubling operation step further includes a step of signal stabilization after the step of receiving said input signal.
In accordance with another aspect of the present invention there is provided a multistage frequency multiplier comprising in a series configuration:
(a) an input network for receiving an input signal having a fundamental frequency component of f0 and for providing impedance matching to said fundamental frequency component;
(b) a plurality of n frequency doublers, to derive from the input signal an output signal having an output frequency component of 2nf0,
wherein each frequency doubler, hereby referred to as a kxe2x80x2 th doubler k less than n, comprises
means for receiving a kxe2x80x2 th input signal having an input frequency component of 2(k-1)f0, and deriving from said input signal a kxe2x80x2 th intermediate signal having a harmonic frequency component of 2kf0, and
means for suppressing said input frequency component from the intermediate signal;
(c) a plurality of n-1 interstage networks, each positioned between a pair of adjacent kxe2x80x2 th and (k+1)xe2x80x2th frequency doublers to provide an interstage impedance matching to the harmonic frequency component 2kf0; and
(d) an output network for impedance matching to the output frequency component of 2nf0.
In one embodiment of this invention, n=2 such that when a fundamental frequency signal is applied to the input network means, a fourth harmonic signal is provided by the output network means. In another embodiment, n=3 such that when a fundamental frequency signal is applied to the input network means, an eighth harmonic signal is provided by the output network means.
In an embodiment of this invention, the frequency doubler comprises a three-terminal transistor device, which can be either a field effect transistor (FET) or a high electron mobility transistor (HEMT). Preferably, the suppressing means is a quarter-wavelength open-ended stub positioned from the transistor device output terminal by an electrical length suitable to provide a most effective suppression of the input frequency component of 2(k-1)f0 and a most effective generation of the harmonic frequency component of 2kf0. Practically, in many cases the electrical length is substantially zero. Also practically, the transmission line is a microstrip line which has electrical parameters which include characteristic impedance and electrical length, that are so selected as to achieve interstage impedance matching by making a pair of reflection coefficients thereof seen in opposite directions to one another have phases of substantially the same values and opposite polarities. Optionally the characteristic impedance is substantially 50 ohms. Yet another embodiment of this invention further comprises stabilization means at the input port, preferably formed of a shunt resistor.
This invention provides interstage matching within a multistage frequency multiplier, without a need for driving amplifiers between doublers therein. One advantage of the present invention is to simplify the circuit topology because the stubs for impedance matching are eliminated, resulting also in a reduction in the total size of the circuits. Another advantage is that when a cascading doubler uses medium power three-terminal transistors, drive power levels can be increased keeping the bandwidth from getting narrow, thereby providing the output power level required from a local oscillator. The apparatus and method of the invention are of particular use in high-speed, large-capacity communications systems and in microwave and millimeter-wave radar transmitters.